1. Field of the Invention
This invention relates to a semiconductor device, particularly a MOS transistor structure whose source and drain are formed as high-concentration diffusion layers (active layers) of shallow depth, and to a method of fabricating the semiconductor device.
2. Description of the Related Art
To suppress the short-channel effect that arises with increasingly fine semiconductor device geometry, the source and drain of a MOS transistor, for example, have in recent years been formed as high-concentration diffusion layers that constitute active layers of shallow depth.
The conventional method of fabricating an N-channel MOS transistor (hereinafter called an "N-type MOS transistor") using such high-concentration diffusion layers (active layers) of shallow depth as the source and drain will be explained using the sectional views of FIGS. 25-30 and the plan view of FIG. 31.
FIGS. 25-30 are sectional views showing the conventional N-type MOS transistor fabricating method in the order of the steps. FIG. 31 is a plan view showing the surface pattern of the N-type MOS transistor. Further, FIG. 32 is a graph showing the junction breakdown voltage between the drain and well of a conventional N-type MOS transistor evaluated in terms of distance between the edge of the device region and contact holes.
The following explanation, which centers on the fabrication steps for the source and drain of the N-type MOS transistor, is presented as an explanation of the method for fabricating the structure of a conventional semiconductor device of this type.
First, as shown in FIG. 25, a P-type diffusion layer of low impurity concentration (hereinafter called a "P well") 2 is formed on a semiconductor substrate 1 and a field oxide film 3 is further formed around the device region 14.
Next, a gate insulating film 4 is formed on the surface of the device region 14. Following this, a polycrystalline silicon film 5 is formed to a prescribed thickness over the whole surface of the semiconductor substrate 1 by the chemical vapor deposition process (hereinafter called the "CVD process").
Next, as shown in FIG. 26, phosphorus, an N-type impurity, is added to the whole surface of the polycrystalline silicon film 5 by ion implantation to form a polycrystalline film 5' added with N-type impurity.
Photoresist is formed over the whole surface by spin coating, and exposure using a prescribed photomask and development are effected to pattern a photoresist 6 in the shape of a gate.
Next, the polycrystalline film 5' is etched by anisotropic etching using the patterned photoresist 6 as an etching mask to pattern a gate 7 as shown in FIG. 27. The photoresist 6 is then removed.
Using an oxidation-diffusion furnace, thermal oxidation is then effected at a temperature of 900.degree. C. for 30 minutes in an oxygen atmosphere to form a mask oxide film 8 composed of a silicon oxide film (SiO.sub.2) on the surface of the gate 7, as shown in FIG. 28.
To form a source and a drain, an impurity of N-type conductivity (such as arsenic (As)) is added to regions of the device region 14 aligned on opposite sides of the gate 7 of the semiconductor substrate 1 (regions between the gate 7 and the field oxide film 3) by ion implantation to form doped layers 9 of N-type conductivity.
Next, as shown in FIG. 29, a silicon oxide-type interlevel insulator film 10 is formed over the whole surface by the CVD process.
The impurity of the N-type doped layers 9 is then activated by effecting annealing in a nitrogen atmosphere.
This results in the formation of N-type high-concentration diffusion layers 11, 11 constituting the source and drain of the N-type MOS transistor.
The interlevel insulator film 10 is then patterned by effecting anisotropic etching of prescribed portions to form contact holes 12, 12, as shown in FIG. 30.
Interconnecting electrodes 13, 13 composed of aluminum are then formed through the contact holes 12, 12 to contact the high-concentration diffusion layers 11, 11 constituting the source (S) and the drain (D), thereby completing an N-type MOS transistor. A contact hole 12 and an interconnecting electrode 13 are also formed with respect to the gate 7 (G) at a location that does not appear in the sectional view of FIG. 30.
The plan view of FIG. 31 shows the surface pattern of the N-type MOS transistor having the high-concentration diffusion layers 11 that was fabricated by the conventional fabrication method explained with reference to FIGS. 25-30. The mask oxide film 8, interlevel insulator film 10, high-concentration diffusion layers 11 and the interconnecting electrodes 13 shown in FIG. 30 are omitted from the plan view of FIG. 31.
FIGS. 30 and 31 show the structure of a conventional N-type MOS transistor having high-concentration diffusion layers 11 of shallow depth as its source and drain.
The solid line in FIG. 31 indicates the inner edge portion 3b of the field oxide film 3 and the rectangle defined by the phantom line outward thereof indicates the outer peripheral portion of the device region 14.
The value of distance X in FIG. 31 is that between the edge portion of the device region 14 and the contact holes 12 and serves as a reference when evaluating the junction breakdown voltage between the drain and well of the N-type MOS transistor.
The variation in the junction breakdown voltage between the drain and well of the N-type MOS transistor with distance between the edge portion of the device region 14 and the contact holes 12 is shown by the graph of FIG. 32.
The horizontal axis of the graph of FIG. 32 represents the distance (.mu.m) between the edge portion of the device region and the contact holes in the N-type MOS transistor, i.e., values corresponding to the distance X shown in FIG. 31, and the vertical axis represents the junction breakdown voltage (V) between the drain and well.
As is clear from this figure, the junction breakdown voltage between the drain and well of the N-type MOS transistor formed by the prior art method described above is strongly dependent on the distance between the edge portion of the device region and the contact holes.
This is because, as shown in FIG. 29, in the N-type MOS transistor whose source and drain are formed as high-concentration diffusion layers 11 of shallow depth by the prior art fabrication method, impurity cannot be implanted in the portion under the bird's beak 3a of thin oxide film at the peripheral portion of the field oxide film 3, so that the high-concentration diffusion layers 11 to become the source and drain cannot be formed here.
Therefore, if the distance X shown in FIG. 31 becomes small owing to formation of the contact holes 12 out of alignment with the prescribed locations within the device region 14, the contact holes 12 will have portions formed as far as the bird's beak 3a of the field oxide film 3 and the interconnecting electrodes 13 shown in FIG. 30 formed in the contact holes 12 will directly contact the P well 2 or the semiconductor substrate 1 without any intervening doped layer.
As a result, unnecessary current will flow within the semiconductor substrate 1 including the P well 2, making it difficult to control normal operation of the N-type MOS transistor.